A systolic fft architecture for real time fpga systems,” high performance embedded computing conference (hpec04

MIT Lincoln Laboratory has recently developed a new systolic FFT architecture for FPGAs. This architec-ture utilizes a parallel design to provide high throughput and excellent numerical accuracy. Using this design, an 8192-point real-time FFT, operating at 1.2 billion sam-ples per second and performing 78 Gops with 70 dB of accuracy, fits on a single Xilinx Virtex II 8000. Key